VHDL Subtelities

1. What is the difference between the following code snippets?

(a)
architecture RTL of tbcount is
signal count: integer := 0;
begin
tb_count : process (clk) is
begin
if rising_edge(clk) then
count <= count + 1;
end if;
end process tb_count;
tbcount <= count;
end architecture RTL;

(b)
architecture RTL of tbcount is
signal count: integer := 0;
begin
tb_count : process (clk) is
begin
if rising_edge(clk) then
count <= count + 1;
end if;
                        tbcount <= count;
end process tb_count;
end architecture RTL;

Solution:

(a) In this case, count will be updated on the rising edge. tbcount will updated delta clock period after the rising edge.
(b) In this case, tbcount will be updated on the falling edge. count gets updated on rising edge, tbcount gets updated on falling edge.

process (clk) has events both on rising edge and falling edge. The events happen both on rising and falling edge, in