Step 2b: Write VHDL Code for 2-to-4 binary decoder

library ieee;
use ieee.std_logic_1164.all;

entity Decodervvhdl is
    port (
        w            :    in        std_logic_vector(1 downto 0);
        y            :    out        std_logic_vector(3 downto 0);
        en            :     in        std_logic
    );
end entity Decodervvhdl;

architecture RTL of Decodervvhdl is
    signal Enw : std_logic_vector(2 downto 0);
    
begin

Enw <= en & w ;
decoder : with Enw select
    y <=
        "0001" when "100",
        "0010" when "101",
        "0100" when "110",
        "1000" when "111",
        "0000" when others;

end architecture RTL;

Synthesized Circuit of VHDL Code in Xilinx ISE:
The interesting aspect of this circuit is that FPGA Synthesizer use RAM module for decode operation.

Test Bench:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.Std_Logic_Unsigned.all ;
use IEEE.Std_Logic_Arith.all;
use work.simpkg.all;
use std.textio.all;

entity tb_decoder is
end tb_decoder;

architecture Test of tb_decoder is
-- Declare/Import DUT
component Decodervvhdl
    port(w  : in  std_logic_vector(1 downto 0);
         y  : out std_logic_vector(3 downto 0);
         en : in  std_logic);
end component Decodervvhdl;
-- Declare Internal Signals which act as Input and Output to DUT
    signal clk : std_logic;     --- clock driver signal

-- Constants ---
    constant period     : time := 10 ns;
    constant update     : time := 1 ns;
    signal w : std_logic_vector(1 downto 0);
    signal y : std_logic_vector(3 downto 0);
    signal en : std_logic;

--Start of Test Bench
begin

-- Define the Clock required for simulation --
testbenchclk : process
begin
    clk <= '0';
    wait for period / 2;
    clk <= '1';
    wait for period / 2;
end process testbenchclk;

-- Instantiate DUT -----
dut:component Decodervvhdl
    port map(w  => w,
             y  => y,
             en => en);

-- Stim Loop --
 stim_loop : process
 variable expected: integer:=1;

 begin
     for i in 0 to 3 loop
         -- Apply Stim to DUT Inputs & update
             w <= CONV_STD_LOGIC_VECTOR(i,2);
             en <= '1';
         wait for update ;
         
         
         --- Check DUT response
         assert (y = CONV_STD_LOGIC_VECTOR(expected,4)) 
              report "Test Failed" &
              "stimulus =" & vec2str(w)    &
              "dut. response =" & vec2str(y) &
              "expected.response="& vec2str(CONV_STD_LOGIC_VECTOR(expected,4))
              severity error;
              
         --- Next Expected response
         expected := expected*2;
         

         -- Next Stim after a delay
         wait for period;    
     end loop;
     wait ;
 end process stim_loop;

--End of Test Bench --
end architecture Test;