Using Packages in VHDL

Today, I was playing with code to write 2 x 2 multiplier. In the process of writing code for the multiplier, I had to use couple of full adders and half adders. Normally, I would write code for the full adder and half adder in separate files and declare them as components in my main file.

Code Style #1: mult2x2.vhd

library ieee;
use ieee.std_logic_1164.all;
use work.adderpackage.all;

entity mult2x2 is
    port (
        A,B    :    in        std_logic_vector(1 downto 0);
        P    :    out        std_logic_vector (3 downto 0)
    );
end entity mult2x2;

architecture RTL of mult2x2 is
    signal p00,p10,p01,p11: std_logic;
    signal c1,c2:std_logic;
    
    --- Full Adder Circuit
    component fa
        port(a, b, cin : in  std_logic;
             s, cout   : out std_logic);
    end component fa;
    
-- Half Adder Circuit
    component ha
        port(a, b    : in  std_logic;
             s, cout : out std_logic);
    end component ha;
begin

p00 <= A(0) and B(0);
p01 <= A(1) and B(0);
p10 <= A(0) and B(1);
p11 <= A(1) and B(1);

P(0) <= p00;
S0:component ha
    port map(a    => p01,
             b    => p10,
             s    => P(1),
             cout => C1);
             
S2:component ha
    port map(a    => C1,
             b    => p11,
             s    => P(2),
             cout => c2);
P(3) <= c2;

end architecture RTL;

However, adding the component instantiations into the main code makes the code look bloated. To simply the code, we can put the component declaration into packages (very similar to header file) and import the package (header file) into main code.

The code below shows how it is done:
Coding Style #2: Mult 2x2

library ieee;
use ieee.std_logic_1164.all;
use work.adderpackage.all;

entity mult2x2 is
    port (
        A,B    :    in        std_logic_vector(1 downto 0);
        P    :    out        std_logic_vector (3 downto 0)
    );
end entity mult2x2;

architecture RTL of mult2x2 is
    signal p00,p10,p01,p11: std_logic;
    signal c1,c2:std_logic;
begin

p00 <= A(0) and B(0);
p01 <= A(1) and B(0);
p10 <= A(0) and B(1);
p11 <= A(1) and B(1);

P(0) <= p00;
S0:component ha
    port map(a    => p01,
             b    => p10,
             s    => P(1),
             cout => C1);
             
S2:component ha
    port map(a    => C1,
             b    => p11,
             s    => P(2),
             cout => c2);
P(3) <= c2;

end architecture RTL;

adderpackage.vhd

library ieee;
use ieee.std_logic_1164.all;

package adderpackage is

--- Full Adder Circuit
  component fa
    port(a, b, cin : in  std_logic;
       s, cout   : out std_logic);
  end component fa;
  
-- Half Adder Circuit
  component ha
    port(a, b    : in  std_logic;
       s, cout : out std_logic);
  end component ha;
    
end package adderpackage;

package body adderpackage is
  
end package body adderpackage;