Step2a: Design of Flipflip using NOR gates in VHDL

I was reading about flip-flops in digital design yesterday. It was intriguing as how feedback circuits of gates can form a flip-flop.

Here is VHDL Code for a flip-flop:

First Attempt:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SRFlipflop is
port 
(
    set,reset     : in std_logic;
    q, q_not     : in std_logic
);
end SRFlipflop;

architecture Behavioral of SRFlipflop is
component nor_component
    port(a, b : in  std_logic;
         y    : out std_logic);
end component nor_component;
begin

n_1:entity work.nor_component
    port map(a => set,
             b => q,
             y => q_not);
             
n_2:component nor_component
    port map(a => q_not,
             b => reset,
             y => q);


end Behavioral;

Errors: 
COMP96 ERROR COMP96_0413: "Actual of mode 'in' cannot be assigned to formal "y" of mode 'out'." "C:\Users\kvemishe\Documents\FPGA\Xilinx Course\SimpleLatch\SRFlipflop.vhd" 23 13

Second Attempt:
To fix the above problem, we make q, and qnot as "inout" rather than "out only

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SRFlipflop is
port 
(
    set,reset     : in std_logic;
    q, q_not     : inout std_logic
);
end SRFlipflop;

architecture Behavioral of SRFlipflop is
component nor_component
    port(a, b : in  std_logic;
         y    : out std_logic);
end component nor_component;
begin

n_1:entity work.nor_component
    port map(a => set,
             b => q,
             y => q_not);
             
n_2:component nor_component
    port map(a => q_not,
             b => reset,
             y => q);


end Behavioral;