Curious Questions: Q1

1. What is the difference between these two codes
Code 1:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFlipFlop is
port 
(
    clk,D,ResetN     : in std_logic;
    Q                 : out std_logic
);
end DFlipFlop;

architecture Behavioral of DFlipFlop is

begin
DFlipFlop : process (clk,ResetN)
begin
if (resetn = '0') then
    Q <= '0';
    elsif    rising_edge(clk) then
    Q <= D;
end if;
--
end process DFlipFlop;


end Behavioral;

Code 2:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFlipFlop is
port 
(
    clk,D,ResetN     : in std_logic;
    Q                 : out std_logic
);
end DFlipFlop;

architecture Behavioral of DFlipFlop is

begin
DFlipFlop : process (clk,ResetN)
begin
    if rising_edge(clk) then
        if (ResetN = '0') then
            Q <='0';
        else
            Q <= D;
        end if;
    end if;

end process DFlipFlop;


end Behavioral;

Investigation so far:

Synthesized Circuit for Code 1

Synthesized Circuit for Code 2

Notice that one has FDC and other is FDR. What is the difference between them?