Step 2e. Bit shifting in VHDL

Today, I was playing with bit shifting to write test bench. The DUT had an input shift register, to apply the input I had to play with shifting operations

1) sra, srl etc.,

For a while, I had trouble getting it to work.

variable temp: std_logic_vector (3 downto 0);

stim := stim sra 1;

I was getting all kinds of errors when I compile. Finally, I found from this wesite that

a) Include use.ieee.numeric_bit.all;

variable temp: bit_vector(3 downto 0);

stim := stim sra 1;

Now it started compiling. I wonder now, is there a way to get std_logic_vector working with sra, sla.

To convert bit to std_ulogic use

to_stdulogic(stim(0));