Books

1. Real Chip Design and Verification using Verilog and VHDL by Ben Cohen

Good Code Snippets

Good Code Snippets
http://labs.det3.net/research/vhdl-code.html

Advanced FPGA Design Concepts

Today, I have learned a new fpga design concept called "Flancter". Clyde introduced this in the VHDL class.

While searching about this on google, I found couple of interesting links:
http://www.doulos.com/knowhow/fpga/fastcounter/

Books related to this topic:
Real Chip Design and Verification using Verilog and VHDL

Using Arrays and For Loop- Example 1

library ieee;
use ieee.std_logic_1164.all;

entity sum_of_squares is
port (
clk : in std_logic;
rst : in std_logic
);
end entity sum_of_squares;

architecture RTL of sum_of_squares is

type onedarrint is array(integer range<>) of real;

procedure sum_squares(inputarr: in onedarrint; result: out real) is
variable acc: real := 0.0;
begin
for i in inputarr'range loop
acc:= acc + (inputarr(i)*inputarr(i));
end loop;
result := acc;
end procedure sum_squares;

begin
testprocedure : process is
variable variations: onedarrint(0 to 100);
variable sum: real;
begin
-- Initialize array
for i in  variations'range loop
variations(i):= real(i);
end loop;

sum_squares(variations,sum);
wait;
end process testprocedure;

VHDL Tips and Tricks

1. Sensitivity List for combinatorial process

Assembling the sensitivity list for a combinatorial  process can be a problem some times. A handy trick in this case is to use "all"

Lengthy way:
fsm: process(clk, in1, in2, next_state)

\....


Easier Way:
fsm: process(all)

2. with select and when-else

Advanced Concepts in VHDL

1. Linked Lists in VHDL
2.

Cool Projects to Work On:
1. Network based projects
2. CPU Design on FPGA

Simulation of Xilinx Components

Recently, I was trying to VHDL COde simulated and I was getting errors

ERROR:HDLCompiler:607 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 340: Multiple declarations of srl16e included via multiple use clauses; none are made directly visible
ERROR:HDLCompiler:40 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 340: srl16e is not a component
ERROR:HDLCompiler:607 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 375: Multiple declarations of dcm_clkgen included via multiple use clauses; none are made directly visible
ERROR:HDLCompiler:40 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 375: dcm_clkgen is not a component
ERROR:HDLCompiler:607 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 401: Multiple declarations of pll_base included via multiple use clauses; none are made directly visible
ERROR:HDLCompiler:40 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 401: pll_base is not a component


Solution:

1) Compile All Simulation Libraries for Model sim






Then double click on "Compile HDL Simulation Libraries"

2) Use in your code
 library UNISIM;
  -- use UNISIM.all;
 use UNISIM.Vcomponents.all;

don't use
 library UNISIM;
  use UNISIM.all;
 use UNISIM.Vcomponents.all;