Tuesday, November 19, 2013

VHDL Tips and Tricks

1. Sensitivity List for combinatorial process

Assembling the sensitivity list for a combinatorial  process can be a problem some times. A handy trick in this case is to use "all"

Lengthy way:
fsm: process(clk, in1, in2, next_state)

\....


Easier Way:
fsm: process(all)

2. with select and when-else

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