Xilinx Netlist Generation from Command Prompt

1. VHDL Files
http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/command_line9.html

2. Verilog Files
http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/command_line10.html

e.g.,
cd <path>
xst
run -ifn timing.v -ifmt Verilog -ofn timingtest.ngc
-ofmt NGC -p XC6SLX45-CSG324-3 -opt_mode Speed -opt_level 1