DCM on Spartan 6

http://beyondallrepair.com/2012/05/dcms-and-clock-division-on-the-xilinx-spartan6-fpga/

More details about DCM SPI Interface:
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

Look in page 83-85

***Note: For DCM SPI Interface, data to be sent should be M-1 and N-1


For example, if input frequency is 100MHz and output frequency required is 10MHz.

Multiply Factor = 1
Divide Factor = 10

So, for SPI Interface send M=0, D=9 (i.e., -1 values)

PLL:

PLL Settling Time (PLL_Locked becoming high from reset) depends on the output frequency selected.
Lower the output frequency, longer the settling time.