Advanced Concepts in VHDL

1. Linked Lists in VHDL
2.

Cool Projects to Work On:
1. Network based projects
2. CPU Design on FPGA

Simulation of Xilinx Components

Recently, I was trying to VHDL COde simulated and I was getting errors

ERROR:HDLCompiler:607 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 340: Multiple declarations of srl16e included via multiple use clauses; none are made directly visible
ERROR:HDLCompiler:40 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 340: srl16e is not a component
ERROR:HDLCompiler:607 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 375: Multiple declarations of dcm_clkgen included via multiple use clauses; none are made directly visible
ERROR:HDLCompiler:40 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 375: dcm_clkgen is not a component
ERROR:HDLCompiler:607 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 401: Multiple declarations of pll_base included via multiple use clauses; none are made directly visible
ERROR:HDLCompiler:40 - "C:/NIFPGA/jobs/EbLbVJ6_F5S06ap/TestAtlys/../Atlys.vhd" Line 401: pll_base is not a component


Solution:

1) Compile All Simulation Libraries for Model sim






Then double click on "Compile HDL Simulation Libraries"

2) Use in your code
 library UNISIM;
  -- use UNISIM.all;
 use UNISIM.Vcomponents.all;

don't use
 library UNISIM;
  use UNISIM.all;
 use UNISIM.Vcomponents.all;